Low temperature 12 ns DRAM

W. H. Henkels*, N. C.C. Lu, Wei Hwang, T. V. Rajeevakumar, R. L. Franch, K. A. Jenkins, T. J. Bucelot, D. F. Heidel, M. J. Immediato

*Corresponding author for this work

Research output: Contribution to conferencePaper

2 Scopus citations

Abstract

Results are presented of measurements on cryogenic operation of a high-speed 512-kb CMOS dynamic RAM (DRAM). Comprehensive investigations focused on circuit concerns particularly relevant to high speed. The measured access time was 12 ns, and the results show that noise, power, and soft error rate do not preclude very-high-speed DRAM operation at cryogenic temperatures. Compared to room-temperature operation the observed improvement in access time was about 1.7× for VDD = 5 V. Compared to 85°C operation the improvement was 2.2×.

Original languageEnglish
Pages32-35
Number of pages4
StatePublished - 1 Dec 1989
EventInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan
Duration: 17 May 198919 May 1989

Conference

ConferenceInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers
CityTaipei, Taiwan
Period17/05/8919/05/89

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    Henkels, W. H., Lu, N. C. C., Hwang, W., Rajeevakumar, T. V., Franch, R. L., Jenkins, K. A., Bucelot, T. J., Heidel, D. F., & Immediato, M. J. (1989). Low temperature 12 ns DRAM. 32-35. Paper presented at International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers, Taipei, Taiwan, .