Low switching noise and load-adaptive output buffer design techniques

Shyh-Jye Jou*, Shu Hua Kuo, Jui Ta Chiu, Tin Hao Lin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

31 Scopus citations

Abstract

Switching noise due to di/dt is becoming severe as technology scales, resulting in a great need for noise-suppression techniques. Several techniques to reduce the switching noise caused by output buffers in CMOS chips are described. An ac/dc output buffer design technique is proposed that includes an innovative feedback mechanism to reduce switching noise and output signal ringing while at the same time maintains timing and dc current requirement. Also, a technique of adaptively separated simultaneous switching noise is proposed that can increase the number of simultaneously switching outputs per VDD and GND pair. Measurement results show that the ac/dc buffer can reduce the output ringing by 2.5× and VDD/GND line bounce by 1.7× and the ASN can double the number of simultaneous switching outputs under the same conditions as compared to the weighted and distributed buffer.

Original languageEnglish
Pages (from-to)1239-1249
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume36
Issue number8
DOIs
StatePublished - 1 Aug 2001

Keywords

  • Buffer
  • Load-adaptive
  • Noise

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