Low-power techniques for network security processors

Yi-Ping You*, Chun Yen Tseng, Yu Hui Huang, Po Chiun Huang, Ting Ting Hwang, Sheng Yu Hsu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.

Original languageEnglish
Title of host publicationProceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages355-360
Number of pages6
DOIs
StatePublished - 1 Dec 2005
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: 18 Jan 200521 Jan 2005

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume1

Conference

Conference2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CountryChina
CityShanghai
Period18/01/0521/01/05

Fingerprint Dive into the research topics of 'Low-power techniques for network security processors'. Together they form a unique fingerprint.

Cite this