This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of 27 - 1, 210 - 1, 215 - 1, 223 -1, and 231 -1 b according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 psrms, and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18-μm CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators.
|Number of pages||7|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - 1 Jul 2008|
- Clock multiplier unit (CMU)
- Parallel feedback shift register (PFSR)
- Psuedorandom word generator (PRWG)