In this paper, a novel low power on-chip current monitor is proposed for adaptive voltage control (AVC). Instead of tracking the delay of worst case critical path replica, current characteristic of target circuits is considered. The proposed current monitor distinguishes between the switching and stable state of the circuit by monitoring the current consumption. It has no negative impact on circuit speed with only less than 3νW power overhead. Using proposed low power on-chip current monitor, a medium-grained adaptive voltage control scheme is also presented. Traditional AVC applied a single (scaled) voltage satisfying critical path to the whole chip, wasting the power in non-critical paths. The medium-grained AVC exploits the unused slack in non-critical paths, which further discovers the power reduction potentiality that lies on non-critical paths. A different width multipliers example exhibits over 30% power reduction on non-critical paths. Simulations are all implemented in Berkeley Predictive 65nm technology .
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 27 Sep 2007|
|Event||2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States|
Duration: 27 May 2007 → 30 May 2007