Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash

Shantanu Rajwade*, Wing Kei Yu, Sarah Xu, Tuo-Hung Hou, G. Edward Suh, Edwin Kan

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper presents a new nonvolatile SRAM design that incorporates low-voltage nanocrystal PMOS Flash transistors. The design enables global store, restore and erase operations with negligible penalty on regular SRAM operation. Store/erase operations also do not consume much power even considering charge pump circuits. Circuit simulations based on experimental I-V characteristics demonstrate that 10 s store/erase operation at 6 Vis sufficient for correct restoration of the stored bit even under reasonable process variation.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2010
Pages461-466
Number of pages6
DOIs
StatePublished - 1 Dec 2010
Event23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States
Duration: 27 Sep 201029 Sep 2010

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference23rd IEEE International SOC Conference, SOCC 2010
CountryUnited States
CityLas Vegas, NV
Period27/09/1029/09/10

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