Low-power multirate IF digital frequency down converter

Shyh-Jye Jou*, Shou Yang Wu, Chorng Kuang Wang

*Corresponding author for this work

Research output: Contribution to journalConference article

Abstract

The architecture design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. Design application for IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6mW when operates at 2 V.

Original languageEnglish
Pages (from-to)231-234
Number of pages4
JournalInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
DOIs
StatePublished - 1 Jan 1999
EventProceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan
Duration: 7 Jun 199910 Jun 1999

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