This brief proposes one-write-one-read (1W1R) and two-write-two-read (2W2R) multiport (MP) SRAMs for register file applications in nanoscale CMOS technology. The cell features a cross-point Write word-line structure to mitigate Write Half-Select disturb and improve the static noise margin (SNM). The Write bit-lines (WBLs) and Write row-access transistors are shared with adjacent bit-cells to reduce the cell transistor count and area. The scheme halves the number of WBL, thus reducing WBL leakage and power consumption. In addition, column-based virtual VSS control is employed for the Read stack to reduce the Read power consumption. Post-sim results show that the proposed scheme reduces both Write/Read current consumption by over 30% compared with the previous MP structure. The proposed scheme is demonstrated and validated by an 8-Kb 2W2R SRAM test chip fabricated in TSMC 40-nm CMOS technology.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - 1 Jan 2014|
- Multiport SRAM
- Read path
- Two-port (TP)