An architecture synthesizer for FIR filter based on CSD code is presented. Traditional filter synthesis tool only generates one set of coefficient that fits the filter specifications. However, in the time and frequency optimization of the filter coefficients, our synthesizer can obtain as many sets of coefficient as possible. The coefficient set that leads to minimum hardware complexity will be selected. Four structures that range is from the fastest speed to the least area can be selected by user. Finally, a synthesizable Verilog code will be automatically generated. A design example that the FIR has 35 taps with 8-bit coefficients shows that the overall hardware reduction by using our synthesizer is 58% as compared to the original design.