Low-power instruction cache architecture using pre-tag checking

Shi You Cheng*, Juinn-Dar Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In this paper, we propose a low-power instruction cache architecture utilizing three techniques two-phased cache, sequential access indicator for tag-memory access skipping, and a new proposed technique namedpre-tag checking. By these techniques, significant portion of tag-memory and data-memory accesses can be eliminated to reduce the power consumption. The experimental results show that the proposed instruction cache architecture can reduce about 54% power consumption compared to the conventional one for an 8KB two-way set associative cache.

Original languageEnglish
Title of host publication2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs
StatePublished - 28 Sep 2007
Event2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan
Duration: 25 Apr 200727 Apr 2007

Publication series

Name2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
CountryTaiwan
CityHsinchu
Period25/04/0727/04/07

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    Cheng, S. Y., & Huang, J-D. (2007). Low-power instruction cache architecture using pre-tag checking. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers [4239408] (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2007.373216