@inproceedings{1d7a44f2adf543d9b3a161dc9ab0002a,
title = "Low-power floating bitline 8-T SRAM design with write assistant circuits",
abstract = "Low power SRAM plays a key important role on SoC designs. In this paper, low-power floating bitline Read/Write scheme and Write assistant circuits are proposed. Read/Write replica circuits are also designed for wide-voltage range operations. A 32-Kb SRAM subarray is implemented in UMC 90nm CMOS technology. It can operate at 1GHz when Vdd is 1V and at 143MHz when Vdd is 0.5V. Moreover, it consumes around 6.6mW to 670uW during access cycles.",
author = "Yang, {Hao I.} and Lai, {Ssu Yun} and Wei Hwang",
year = "2008",
month = dec,
day = "1",
doi = "10.1109/SOCC.2008.4641519",
language = "English",
isbn = "9781424425969",
series = "2008 IEEE International SOC Conference, SOCC",
pages = "239--242",
booktitle = "2008 IEEE International SOC Conference, SOCC",
note = "null ; Conference date: 17-09-2008 Through 20-09-2008",
}