Low-power floating bitline 8-T SRAM design with write assistant circuits

Hao I. Yang*, Ssu Yun Lai, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Low power SRAM plays a key important role on SoC designs. In this paper, low-power floating bitline Read/Write scheme and Write assistant circuits are proposed. Read/Write replica circuits are also designed for wide-voltage range operations. A 32-Kb SRAM subarray is implemented in UMC 90nm CMOS technology. It can operate at 1GHz when Vdd is 1V and at 143MHz when Vdd is 0.5V. Moreover, it consumes around 6.6mW to 670uW during access cycles.

Original languageEnglish
Title of host publication2008 IEEE International SOC Conference, SOCC
Pages239-242
Number of pages4
DOIs
StatePublished - 1 Dec 2008
Event2008 IEEE International SOC Conference, SOCC - Newport Beach, CA, United States
Duration: 17 Sep 200820 Sep 2008

Publication series

Name2008 IEEE International SOC Conference, SOCC

Conference

Conference2008 IEEE International SOC Conference, SOCC
CountryUnited States
CityNewport Beach, CA
Period17/09/0820/09/08

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    Yang, H. I., Lai, S. Y., & Hwang, W. (2008). Low-power floating bitline 8-T SRAM design with write assistant circuits. In 2008 IEEE International SOC Conference, SOCC (pp. 239-242). [4641519] (2008 IEEE International SOC Conference, SOCC). https://doi.org/10.1109/SOCC.2008.4641519