Low-power floating bitline 8-T SRAM design with write assistant circuits

Hao I. Yang; Ssu Yun Lai; Wei Hwang

doi:10.1109/SOCC.2008.4641519

Low-power floating bitline 8-T SRAM design with write assistant circuits

Hao I. Yang^*, Ssu Yun Lai, Wei Hwang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Low power SRAM plays a key important role on SoC designs. In this paper, low-power floating bitline Read/Write scheme and Write assistant circuits are proposed. Read/Write replica circuits are also designed for wide-voltage range operations. A 32-Kb SRAM subarray is implemented in UMC 90nm CMOS technology. It can operate at 1GHz when Vdd is 1V and at 143MHz when Vdd is 0.5V. Moreover, it consumes around 6.6mW to 670uW during access cycles.

Original language	English
Title of host publication	2008 IEEE International SOC Conference, SOCC
Pages	239-242
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2008.4641519
State	Published - 1 Dec 2008
Event	2008 IEEE International SOC Conference, SOCC - Newport Beach, CA, United States Duration: 17 Sep 2008 → 20 Sep 2008

Publication series

Name	2008 IEEE International SOC Conference, SOCC

Conference

Conference	2008 IEEE International SOC Conference, SOCC
Country	United States
City	Newport Beach, CA
Period	17/09/08 → 20/09/08

Access to Document

10.1109/SOCC.2008.4641519

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AB - Low power SRAM plays a key important role on SoC designs. In this paper, low-power floating bitline Read/Write scheme and Write assistant circuits are proposed. Read/Write replica circuits are also designed for wide-voltage range operations. A 32-Kb SRAM subarray is implemented in UMC 90nm CMOS technology. It can operate at 1GHz when Vdd is 1V and at 143MHz when Vdd is 0.5V. Moreover, it consumes around 6.6mW to 670uW during access cycles.

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