Low-power fixed-width array multipliers

Jinn Shyan Wang*, Chien-Nan Kuo, Tsung Han Yang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

A fixed-width multiplier using the left-to-right algorithm for partial-product reduction is presented. The high-speed feature offered by this design is used to trade for low power. In one design, the proposed multiplier not only owns 8% speed improvement but also gains 14% power and 13% area reduction. When applying the voltage scaling to balance the speed, the power reduction is increased to 29%.

Original languageEnglish
Title of host publicationISLPED '04: Proceedings of the 2004 International Symposium on Low Power Electronics and Design
Pages307-312
Number of pages6
DOIs
StatePublished - 1 Dec 2004
Event2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States
Duration: 9 Aug 200411 Aug 2004

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

Conference2004 International Symposium on Low Power Electronics and Design, ISLPED 2004
CountryUnited States
CityNewport Beach
Period9/08/0411/08/04

Keywords

  • Fixed-width multiplier
  • Left-to-right multiplier
  • Low power
  • Reduced-width multiplier

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    Wang, J. S., Kuo, C-N., & Yang, T. H. (2004). Low-power fixed-width array multipliers. In ISLPED '04: Proceedings of the 2004 International Symposium on Low Power Electronics and Design (pp. 307-312). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1109/LPE.2004.241092