Low power encoding schemes for run-time on-chip bus

Po-Tsang Huang*, Wei Hwang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

3 Scopus citations

Abstract

The coupling effect dominates the power consumption during the run-time in on-chip buses. In this paper we present two low power bus encoding design schemes, one-half encoding and two phase encoding, for reducing the coupling effect in SoC interconnects. Minimizing the power consumption is an important issue for on-chip bus in SoC design in deep submicron technology. There are various approaches to reduce the coupling effect, and we focus on the encoding scheme of reduction of transition activities. Applied data streams contain random data, JPFG, MPEG, MP3 and PDF. Our simulation results indicate that our proposed schemes can save the power 36% for one-half encoding scheme and 31% for two phase encoding scheme by using HSPICE of TSMC 100nm technology.

Original languageEnglish
Pages1025-1028
Number of pages4
StatePublished - 1 Dec 2004
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 6 Dec 20049 Dec 2004

Conference

Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period6/12/049/12/04

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