Low Power Dynamic Ternary Logic

A new dynamic ternary logic and its circuit structures have been developed to achieve the goal of low power dissipation and high operation speed. Based on the selected ternary algebra, a dynamic ternary logic system can be implemented by simple ternary gates (STGs), with positive or negative ternary inverters connected to all the input terminals. An overlapped four-phase clocking scheme is needed, and the connection of different circuit blocks has to follow the permitted fan-out diagrams. As compared to the static ternary logic, the dynamic ternary logic has a lower DC power dissipation and an operation mspeed approximately twice as fast. Typical powerdelay product of a simple ternary inverter in 2 fim CMOS is 3 fJ. Moreover, as compared with binary circuits, the ternary circuit has better performances of the powerdelay product and less terminal leads per functional circuit. These features make the dynamic logic circuits quite attractive in VLSI/ULSI applications.