Low-power digital CDMA receiver

Ja Sheng Liu, I. Hsin Chen, Yi Chen Tai, Shyh-Jye Jou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The advanced design tasks for a digital CDMA receiver are presented in this report. A biased number system and architecture are used to reduce the switching activity to reduce power consumption. A carry-save adder tree is used to speed up the summation of 127 data (3 bits) in the synchronization and date extraction process. Verilog HDL is used to describe this system and the design compiler of Synopsys is used to synthesize our design. Design results show that it can work at 155 MHz (chip rate) with 9913 gate counts by using the Compass 0.35 μm CMOS cell library.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages581-582
Number of pages2
ISBN (Electronic)0780376595
DOIs
StatePublished - 1 Jan 2003
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 21 Jan 200324 Jan 2003

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2003-January

Conference

ConferenceAsia and South Pacific Design Automation Conference, ASP-DAC 2003
CountryJapan
CityKitakyushu
Period21/01/0324/01/03

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