Low-power data address bus encoding method

Tsung Hsi Weng*, Wei Hao Chiao, Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Reducing power consumption of computer systems has gained much research attention recently. In a typical system, the memory bus power constitute will over 50% of all system power; and this power is required due to bus signal transitions (0→1 or 1→0). Reducing the number of memory bus transitions is hence an effective way to reduce system power. While many techniques deal with reducing bus power on instruction address bus, only a few have been proposed for data address bus power reduction. We present an encoding scheme to reduce data address bus power consumption. In this scheme, data address bus can be frozen for sequential addresses, or inverted as appropriate for other cases. Furthermore, data addresses are classified into read addresses and write addresses, and each address set is encoded independently. Simulation results show that the overall bus line switching reduction is 26% of unencoded bus, or 14.5% of the previous TO-BI method [1].

Original languageEnglish
Title of host publicationProceedings of the 2005 International Conference on Computer Design, CDES'05
Pages204-210
Number of pages7
StatePublished - 1 Dec 2005
Event2005 International Conference on Computer Design, CDES'05 - Las Vegas, NV, United States
Duration: 27 Jun 200530 Jun 2005

Publication series

NameProceedings of the 2005 International Conference on Computer Design, CDES'05

Conference

Conference2005 International Conference on Computer Design, CDES'05
CountryUnited States
CityLas Vegas, NV
Period27/06/0530/06/05

Keywords

  • Bus encoding
  • Data address bus
  • Low-power
  • T0-BI-1

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