Low-power branch prediction

Yau Chong Hu*, Wei Hau Chiao, Jyh-Jiun Shann, Chung-Ping Chung, Wen Feng Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Low-power design has gained much attention recently, especially for computing on battery-powered equipments. Reducing BTB (branch target buffer) accesses is an effective way to reduce processor power consumption, since BTB consumes a significant portion of power in a processor. In this paper, we propose two approaches to reduce BTB accesses. The first approach expects the distance of every two dynamic branch instructions to be a constant n, where n can be statically profiled, and forces BTB to repose for n instructions after a BTB hit. The second approach dynamically predicts the address of the next branch instruction, and accesses BTB only on the predicted address. Multimedia/DSP benchmarks are used in our evaluation. Experimental results show that these methods can potentially reduce 22.033% of all BTB accesses.

Original languageEnglish
Title of host publicationProceedings of the 2005 International Conference on Computer Design, CDES'05
Pages211-217
Number of pages7
StatePublished - 1 Dec 2005
Event2005 International Conference on Computer Design, CDES'05 - Las Vegas, NV, United States
Duration: 27 Jun 200530 Jun 2005

Publication series

NameProceedings of the 2005 International Conference on Computer Design, CDES'05

Conference

Conference2005 International Conference on Computer Design, CDES'05
CountryUnited States
CityLas Vegas, NV
Period27/06/0530/06/05

Keywords

  • Branch prediction
  • Branch target buffer
  • Low-power

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    Hu, Y. C., Chiao, W. H., Shann, J-J., Chung, C-P., & Chen, W. F. (2005). Low-power branch prediction. In Proceedings of the 2005 International Conference on Computer Design, CDES'05 (pp. 211-217). (Proceedings of the 2005 International Conference on Computer Design, CDES'05).