Low-power BIBITS encoding with register relabeling for instruction bus

Chin Tzung Cheng*, Wei Hau Chiao, Jyh-Jiun Shann, Chung-Ping Chung, Wen Feng Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Reducing power consumption of embedded system has gained much attention recently. Reducing memory bus switchings is an effective way to reduce system power since memory bus power constitutes a great portion of the system power. While many techniques exist for reducing bus power in address buses, only a few have been proposed for content-bus power reduction. We propose a Bus-Invert and Bus-Invert with transition signaling (BIBITS) encoding scheme to reduce power consumption on instruction bus. An instruction is partitioned into fields according to its format. Four elementary Boolean functions are used as encoding functions. BIBITS uses the most suitable encoding functions for different instruction partitions. We also propose a register relabeling algorithm for BIBITS encoding to further reduce bit switchings on register fields. Simulation results show that the overall average switching reduction is 64% of unencoded bus, 59% of the previous register relabeling scheme, and 33% of Petrov's bus encoding scheme. Compared with Petrov's bus encoding scheme, our scheme uses a decoding signal table only half the size to encode all basic blocks.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages41-44
Number of pages4
DOIs
StatePublished - 1 Dec 2005
Event2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
Duration: 27 Apr 200529 Apr 2005

Publication series

Name2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Volume2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
CountryTaiwan
CityHsinchu
Period27/04/0529/04/05

Keywords

  • BIBITS
  • Bus encoding
  • Embedded system
  • Low power
  • Register relabeling

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    Cheng, C. T., Chiao, W. H., Shann, J-J., Chung, C-P., & Chen, W. F. (2005). Low-power BIBITS encoding with register relabeling for instruction bus. In 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) (pp. 41-44). [1500015] (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); Vol. 2005). https://doi.org/10.1109/VDAT.2005.1500015