Low power and reliable interconnection with self-corrected green coding scheme for network-on-chip

Po-Tsang Huang*, Wei Li Fang, Yin Ling Wang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

21 Scopus citations

Abstract

In this paper, a low power joint bus and error correction coding is proposed to provide reliable and energy- efficient interconnection for network-on-chip (NoC) in nanoscale technology. The proposed self-corrected "green" (low power) coding scheme is constructed by two stages, which are triplication error correction coding (ECC) stage and green bus coding stage. Triplication ECC provides a more reliable mechanism to advanced technologies. Moreover, in view of lower latency of decoder, it has rapid correction ability to reduce the physical transfer unit size of switch fabrics by self- corrected technique in bit level. The green bus coding employs more energy reduction by a joint triplication bus power model for crosstalk avoidance. In addition, the circuitry of green bus coding is more simple and effective. Based on UMC 90nm CMOS technology, the simulation results show self-corrected green coding can achieve 34.4% energy reduction with small codec overhead. This approach not only makes the NoC applications tolerant against transient malfunctions, but also realizes energy efficiency.

Original languageEnglish
Title of host publicationProceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008
Pages77-83
Number of pages7
DOIs
StatePublished - 28 May 2008
Event2nd IEEE International Symposium on Networks-on-Chip, NOCS 2008 - Newcastle upon Tyne, United Kingdom
Duration: 7 Apr 200811 Apr 2008

Publication series

NameProceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008

Conference

Conference2nd IEEE International Symposium on Networks-on-Chip, NOCS 2008
CountryUnited Kingdom
CityNewcastle upon Tyne
Period7/04/0811/04/08

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