Low power 900 MHz register file (8 ports, 32 words × 64 bits) IN 1.8 v, 0.25μm SOI technology

R. V. Joshi*, Wei Hwang, S. Wilson, G. Shahidi, C. T. Chuang

*Corresponding author for this work

Research output: Contribution to conferencePaper

3 Scopus citations

Abstract

This paper shows full functionality of a low power 900 MHz dynamic register file (6 Read and 2 Write ports, 32 wordlines × 64 bitlines). Such a register file is designed for bulk silicon technology but is fabricated in 0.25μm Silicon on Insulator (SOI) technology without any body contacts. This paper also proposes a new method to extract the performance gain (which is limited by the tester speed) of a register file in bulk and SOI technology based on internal picoprobe measurements along the critical path. Based on the hardware and simulation data the register file is capable of functioning at 900 MHz for read and write operations in a single cycle. The register file can even function above 1 GHz for read operation. A power reduction of 8-12% is realized for SOI over bulk technology especially at higher frequencies.

Original languageEnglish
Pages44-49
Number of pages6
StatePublished - 1 Jan 2000
EventThe 13th International Conference on VLSI Design: Wireless and Digital Imaging in the Millennium - Calcutta, India
Duration: 3 Jan 20007 Jan 2000

Conference

ConferenceThe 13th International Conference on VLSI Design: Wireless and Digital Imaging in the Millennium
CityCalcutta, India
Period3/01/007/01/00

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    Joshi, R. V., Hwang, W., Wilson, S., Shahidi, G., & Chuang, C. T. (2000). Low power 900 MHz register file (8 ports, 32 words × 64 bits) IN 1.8 v, 0.25μm SOI technology. 44-49. Paper presented at The 13th International Conference on VLSI Design: Wireless and Digital Imaging in the Millennium, Calcutta, India, .