Low-Power 3D-PCB Stacking System Design and Validation by Automatic Voltage-Current Scalable Technique

Ching Hwa Cheng, Jiun In Guo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The proposed design is integrating multiple video and power-regulate chips integrated with a low-power 3D-PCB Stacking system. This performance-power optimized 3D-PCB Stacking SoC system is corroborated by the dual multi-mode video decoder (MMVD) and five voltage-current adjustors (VCAs) chips. Low-power dual-Vdd design techniques are utilized in MMVD, without using level converters. The VCA is used to supply manageable power-current to MMVD. The automated voltage-current adjusted technique does not increase the additional silicon cost without using voltage converters. The low-power contribution is to utilize current-Adjusted technique for an automation voltage-Adjustor. A built-in voltage measurement provides voltage-level can be safely regulated.The system achieves a 32 \sim 68% power reduction for two video decoders by using the VCAs. The system scalable function is implemented by a MorPack 3D-PCB stacking design. The proposed technique is success validated reduce system power consumption and without performance degradation.

Original languageEnglish
Title of host publication2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728160832
DOIs
StatePublished - Aug 2020
Event2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 - Hsinchu, Taiwan
Duration: 10 Aug 202013 Aug 2020

Publication series

Name2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020

Conference

Conference2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
CountryTaiwan
CityHsinchu
Period10/08/2013/08/20

Keywords

  • heterogeneous 3D-IC
  • system-in-package

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