Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range

Steve S. Chung*, H. J. Feng, Y. S. Hsieh, Alex Liu, W. M. Lin, D. F. Chen, J. H. Ho, K. T. Huang, C. K. Yang, Osbert Cheng, Y. C. Sheng, D. Y. Wu, W. T. Shiau, S. C. Chien, Kuan Liao, S. W. Sun

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

4 Scopus citations

Abstract

A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12Å-16Å range gate oxide CMOS devices has been demonstrated. The approach being taken includes an incremental frequency Charge-Pumping(IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate determination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.

Original languageEnglish
Pages (from-to)477-480
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
DOIs
StatePublished - 1 Dec 2004
EventIEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
Duration: 13 Dec 200415 Dec 2004

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