Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range

Steve S. Chung; H. J. Feng; Y. S. Hsieh; Alex Liu; W. M. Lin; D. F. Chen; J. H. Ho; K. T. Huang; C. K. Yang; Osbert Cheng; Y. C. Sheng; D. Y. Wu; W. T. Shiau; S. C. Chien; Kuan Liao; S. W. Sun

doi:10.1109/IEDM.2004.1419193

Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range

Steve S. Chung^*, H. J. Feng, Y. S. Hsieh, Alex Liu, W. M. Lin, D. F. Chen, J. H. Ho, K. T. Huang, C. K. Yang, Osbert Cheng, Y. C. Sheng, D. Y. Wu, W. T. Shiau, S. C. Chien, Kuan Liao, S. W. Sun

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Conference article › peer-review

4 Scopus citations

Abstract

A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12Å-16Å range gate oxide CMOS devices has been demonstrated. The approach being taken includes an incremental frequency Charge-Pumping(IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate determination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.

Original language	English
Pages (from-to)	477-480
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting, IEDM
DOIs	https://doi.org/10.1109/IEDM.2004.1419193
State	Published - 1 Dec 2004
Event	IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States Duration: 13 Dec 2004 → 15 Dec 2004

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Chung, S. S., Feng, H. J., Hsieh, Y. S., Liu, A., Lin, W. M., Chen, D. F., Ho, J. H., Huang, K. T., Yang, C. K., Cheng, O., Sheng, Y. C., Wu, D. Y., Shiau, W. T., Chien, S. C., Liao, K., & Sun, S. W. (2004). Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range. Technical Digest - International Electron Devices Meeting, IEDM, 477-480. https://doi.org/10.1109/IEDM.2004.1419193

Chung, Steve S. ; Feng, H. J. ; Hsieh, Y. S. ; Liu, Alex ; Lin, W. M. ; Chen, D. F. ; Ho, J. H. ; Huang, K. T. ; Yang, C. K. ; Cheng, Osbert ; Sheng, Y. C. ; Wu, D. Y. ; Shiau, W. T. ; Chien, S. C. ; Liao, Kuan ; Sun, S. W. / Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range. In: Technical Digest - International Electron Devices Meeting, IEDM. 2004 ; pp. 477-480.

@article{7e908848980148eaba61e8cde275c5fa,

title = "Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range",

abstract = "A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12{\AA}-16{\AA} range gate oxide CMOS devices has been demonstrated. The approach being taken includes an incremental frequency Charge-Pumping(IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate determination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.",

author = "Chung, {Steve S.} and Feng, {H. J.} and Hsieh, {Y. S.} and Alex Liu and Lin, {W. M.} and Chen, {D. F.} and Ho, {J. H.} and Huang, {K. T.} and Yang, {C. K.} and Osbert Cheng and Sheng, {Y. C.} and Wu, {D. Y.} and Shiau, {W. T.} and Chien, {S. C.} and Kuan Liao and Sun, {S. W.}",

year = "2004",

month = dec,

day = "1",

doi = "10.1109/IEDM.2004.1419193",

language = "English",

pages = "477--480",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 13-12-2004 Through 15-12-2004",

}

Chung, SS, Feng, HJ, Hsieh, YS, Liu, A, Lin, WM, Chen, DF, Ho, JH, Huang, KT, Yang, CK, Cheng, O, Sheng, YC, Wu, DY, Shiau, WT, Chien, SC, Liao, K & Sun, SW 2004, 'Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range', Technical Digest - International Electron Devices Meeting, IEDM, pp. 477-480. https://doi.org/10.1109/IEDM.2004.1419193

Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range. / Chung, Steve S.; Feng, H. J.; Hsieh, Y. S.; Liu, Alex; Lin, W. M.; Chen, D. F.; Ho, J. H.; Huang, K. T.; Yang, C. K.; Cheng, Osbert; Sheng, Y. C.; Wu, D. Y.; Shiau, W. T.; Chien, S. C.; Liao, Kuan; Sun, S. W.

In: Technical Digest - International Electron Devices Meeting, IEDM, 01.12.2004, p. 477-480.

Research output: Contribution to journal › Conference article › peer-review

TY - JOUR

T1 - Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range

AU - Chung, Steve S.

AU - Feng, H. J.

AU - Hsieh, Y. S.

AU - Liu, Alex

AU - Lin, W. M.

AU - Chen, D. F.

AU - Ho, J. H.

AU - Huang, K. T.

AU - Yang, C. K.

AU - Cheng, Osbert

AU - Sheng, Y. C.

AU - Wu, D. Y.

AU - Shiau, W. T.

AU - Chien, S. C.

AU - Liao, Kuan

AU - Sun, S. W.

PY - 2004/12/1

Y1 - 2004/12/1

N2 - A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12Å-16Å range gate oxide CMOS devices has been demonstrated. The approach being taken includes an incremental frequency Charge-Pumping(IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate determination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.

AB - A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12Å-16Å range gate oxide CMOS devices has been demonstrated. The approach being taken includes an incremental frequency Charge-Pumping(IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate determination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.

UR - http://www.scopus.com/inward/record.url?scp=21644432897&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2004.1419193

DO - 10.1109/IEDM.2004.1419193

M3 - Conference article

AN - SCOPUS:21644432897

SP - 477

EP - 480

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

Y2 - 13 December 2004 through 15 December 2004

ER -