A new power-rail ESD clamp circuit is proposed and verified with consideration of the gate leakage issue in 65-nm CMOS technology. The proposed circuit can reduce the total leakage current of the traditional power-rail ESD clamp circuit in two orders of magnitude. Moreover, the proposed circuit reduces the required silicon area by boosting the capacitor with a current mirror. The measured leakage current of the proposed power-rail ESD clamp circuit is 220nA (VDD = 1V, T=25°C), much lower than the 20.55μA of the traditional design. In addition, the required area for the proposed design is 50μm × 30μm, which is a 40% reduction in silicon area to the traditional one, that can sustain the HBM (MM) ESD stress of 3.5kV (250V).