Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology

Federico A. Altolaguirre, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A new power-rail ESD clamp circuit is proposed and verified with consideration of the gate leakage issue in 65-nm CMOS technology. The proposed circuit can reduce the total leakage current of the traditional power-rail ESD clamp circuit in two orders of magnitude. Moreover, the proposed circuit reduces the required silicon area by boosting the capacitor with a current mirror. The measured leakage current of the proposed power-rail ESD clamp circuit is 220nA (VDD = 1V, T=25°C), much lower than the 20.55μA of the traditional design. In addition, the required area for the proposed design is 50μm × 30μm, which is a 40% reduction in silicon area to the traditional one, that can sustain the HBM (MM) ESD stress of 3.5kV (250V).

Original languageEnglish
Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages2638-2641
Number of pages4
DOIs
StatePublished - 9 Sep 2013
Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
Duration: 19 May 201323 May 2013

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
CountryChina
CityBeijing
Period19/05/1323/05/13

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