Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Chang Tzu Wang*, Ming-Dou Ker, Tien Hao Tang, Kuan Cheng Su

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49μmx21μm and consuming a very low standby leakage current of 96nA at room temperature.

Original languageEnglish
Title of host publication2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Pages21-24
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 - Austin, TX, United States
Duration: 18 May 200920 May 2009

Publication series

Name2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Conference

Conference2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
CountryUnited States
CityAustin, TX
Period18/05/0920/05/09

Keywords

  • Electrostatic discharge (ESD)
  • Gate leakage
  • Power-rail ESD clamp circuit
  • Silicon controlled rectifier (SCR)

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