Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction

D. Hassan Zadeh, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Ultra-thin InGaAs gate stacks with CET= 0.73 nm (EOT< 0.5 nm), D it as low as 8.0×1011 (cm-2 eV -1) and thermal stability up to 600°C is demonstrated by using La2O3 as gate dielectric. A silicide/InGaAs junction with excellent controllability at the interface is also proposed. These results promise the integration compatibility of this gate stack for future node 3D device structures.

Original languageEnglish
Title of host publication2013 IEEE International Electron Devices Meeting, IEDM 2013
Pages2.4.1-2.4.4
DOIs
StatePublished - 2013
Event2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States
Duration: 9 Dec 201311 Dec 2013

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2013 IEEE International Electron Devices Meeting, IEDM 2013
CountryUnited States
CityWashington, DC
Period9/12/1311/12/13

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    Zadeh, D. H., Oomine, H., Kakushima, K., Kataoka, Y., Nishiyama, A., Sugii, N., Wakabayashi, H., Tsutsui, K., Natori, K., & Iwai, H. (2013). Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction. In 2013 IEEE International Electron Devices Meeting, IEDM 2013 (pp. 2.4.1-2.4.4). [6724544] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2013.6724544