Ultra-thin InGaAs gate stacks with CET= 0.73 nm (EOT< 0.5 nm), D it as low as 8.0×1011 (cm-2 eV -1) and thermal stability up to 600°C is demonstrated by using La2O3 as gate dielectric. A silicide/InGaAs junction with excellent controllability at the interface is also proposed. These results promise the integration compatibility of this gate stack for future node 3D device structures.
|Title of host publication||2013 IEEE International Electron Devices Meeting, IEDM 2013|
|State||Published - 2013|
|Event||2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States|
Duration: 9 Dec 2013 → 11 Dec 2013
|Name||Technical Digest - International Electron Devices Meeting, IEDM|
|Conference||2013 IEEE International Electron Devices Meeting, IEDM 2013|
|Period||9/12/13 → 11/12/13|