Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches

Pei Yuan Chou; I. Chen Wu; Jai Wei Lin; Xuan Yu Lin; Tien-Fu Chen; Tay Jyi Lin; Jinn Shyan Wang

doi:10.1109/ASICON.2015.7517050

Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches

Pei Yuan Chou, I. Chen Wu, Jai Wei Lin, Xuan Yu Lin, Tien-Fu Chen, Tay Jyi Lin, Jinn Shyan Wang

Institute of Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We propose to use a canary circuit with dynamic trip-point sensing scheme to replace ECC check bits and related circuits in conventional DVS caches for reducing area overhead and to enable deeper voltage scaling for reducing power consumption. With the canary circuit, a variable-cycle access controller can easily deal with an overlong delay without pre-allocating Vcc headroom for covering the droop voltage. Applying all the proposed delay-fault-prevention design techniques together can lead to a cost-effective and power-efficient DVS cache.

Original language	English
Title of host publication	Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
Editors	Junyan Ren, Ting-Ao Tang, Fan Ye, Huihua Yu
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479984831
DOIs	https://doi.org/10.1109/ASICON.2015.7517050
State	Published - 21 Jul 2016
Event	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China Duration: 3 Nov 2015 → 6 Nov 2015

Publication series

Name	Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

Conference

Conference	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
Country	China
City	Chengdu
Period	3/11/15 → 6/11/15

Access to Document

10.1109/ASICON.2015.7517050

Link to publication in Scopus

Fingerprint Dive into the research topics of 'Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches'. Together they form a unique fingerprint.

Cite this

Chou, P. Y., Wu, I. C., Lin, J. W., Lin, X. Y., Chen, T-F., Lin, T. J., & Wang, J. S. (2016). Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. In J. Ren, T-A. Tang, F. Ye, & H. Yu (Eds.), Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 [7517050] (Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASICON.2015.7517050

Chou, Pei Yuan ; Wu, I. Chen ; Lin, Jai Wei ; Lin, Xuan Yu ; Chen, Tien-Fu ; Lin, Tay Jyi ; Wang, Jinn Shyan. / Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. editor / Junyan Ren ; Ting-Ao Tang ; Fan Ye ; Huihua Yu. Institute of Electrical and Electronics Engineers Inc., 2016. (Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015).

@inproceedings{8c8ed12404b541db97d6bea5a03914a0,

title = "Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches",

abstract = "We propose to use a canary circuit with dynamic trip-point sensing scheme to replace ECC check bits and related circuits in conventional DVS caches for reducing area overhead and to enable deeper voltage scaling for reducing power consumption. With the canary circuit, a variable-cycle access controller can easily deal with an overlong delay without pre-allocating Vcc headroom for covering the droop voltage. Applying all the proposed delay-fault-prevention design techniques together can lead to a cost-effective and power-efficient DVS cache.",

author = "Chou, {Pei Yuan} and Wu, {I. Chen} and Lin, {Jai Wei} and Lin, {Xuan Yu} and Tien-Fu Chen and Lin, {Tay Jyi} and Wang, {Jinn Shyan}",

year = "2016",

month = jul,

day = "21",

doi = "10.1109/ASICON.2015.7517050",

language = "English",

series = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Junyan Ren and Ting-Ao Tang and Fan Ye and Huihua Yu",

booktitle = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",

note = "null ; Conference date: 03-11-2015 Through 06-11-2015",

}

Chou, PY, Wu, IC, Lin, JW, Lin, XY, Chen, T-F, Lin, TJ & Wang, JS 2016, Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. in J Ren, T-A Tang, F Ye & H Yu (eds), Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7517050, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 3/11/15. https://doi.org/10.1109/ASICON.2015.7517050

Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. / Chou, Pei Yuan; Wu, I. Chen; Lin, Jai Wei; Lin, Xuan Yu; Chen, Tien-Fu; Lin, Tay Jyi; Wang, Jinn Shyan.

Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. ed. / Junyan Ren; Ting-Ao Tang; Fan Ye; Huihua Yu. Institute of Electrical and Electronics Engineers Inc., 2016. 7517050 (Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches

AU - Chou, Pei Yuan

AU - Wu, I. Chen

AU - Lin, Jai Wei

AU - Lin, Xuan Yu

AU - Chen, Tien-Fu

AU - Lin, Tay Jyi

AU - Wang, Jinn Shyan

PY - 2016/7/21

Y1 - 2016/7/21

N2 - We propose to use a canary circuit with dynamic trip-point sensing scheme to replace ECC check bits and related circuits in conventional DVS caches for reducing area overhead and to enable deeper voltage scaling for reducing power consumption. With the canary circuit, a variable-cycle access controller can easily deal with an overlong delay without pre-allocating Vcc headroom for covering the droop voltage. Applying all the proposed delay-fault-prevention design techniques together can lead to a cost-effective and power-efficient DVS cache.

AB - We propose to use a canary circuit with dynamic trip-point sensing scheme to replace ECC check bits and related circuits in conventional DVS caches for reducing area overhead and to enable deeper voltage scaling for reducing power consumption. With the canary circuit, a variable-cycle access controller can easily deal with an overlong delay without pre-allocating Vcc headroom for covering the droop voltage. Applying all the proposed delay-fault-prevention design techniques together can lead to a cost-effective and power-efficient DVS cache.

UR - http://www.scopus.com/inward/record.url?scp=84982279524&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2015.7517050

DO - 10.1109/ASICON.2015.7517050

M3 - Conference contribution

AN - SCOPUS:84982279524

T3 - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

BT - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

A2 - Ren, Junyan

A2 - Tang, Ting-Ao

A2 - Ye, Fan

A2 - Yu, Huihua

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 3 November 2015 through 6 November 2015

ER -

Chou PY, Wu IC, Lin JW, Lin XY, Chen T-F, Lin TJ et al. Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. In Ren J, Tang T-A, Ye F, Yu H, editors, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7517050. (Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015). https://doi.org/10.1109/ASICON.2015.7517050