Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture

Lan-Da Van*, Yuan Chu Yu, Chun Ming Huang, Chin Teng Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

In this paper, we propose two low-computation cycle and high-speed recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architectures adopting the hybrid of Chebyshev polynomial and register-splitting scheme. The proposed core-type recursive architecture achieves half computation-cycle reduction as well as less critical period compared with the conventional second-order DFT/IDFT architecture. So as to further reduce the number of computation cycles, based on the new core-type design, we develop the folded-type recursive DFT/IDFT architecture with the same operating frequency. Moreover, from the derivation results, the operation of DFT and IDFT can be performed with the same structure under different configurations.

Original languageEnglish
Title of host publicationSiPS 2005
Subtitle of host publicationIEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings
Pages579-584
Number of pages6
DOIs
StatePublished - 1 Dec 2005
EventSiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation - Athens, Greece
Duration: 2 Nov 20054 Nov 2005

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Volume2005
ISSN (Print)1520-6130

Conference

ConferenceSiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation
CountryGreece
CityAthens
Period2/11/054/11/05

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