Low-complexity digit-serial multiplier over GF(2m) based on efficient toeplitz block toeplitz matrix-vector product decomposition

Chiou Yng Lee, Pramod Kumar Meher, Chia Chen Fan, Shyan-Ming Yuan

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

In this paper, we have shown that a regular Toeplitz matrix-vector product (TMVP) can be transformed into a Toeplitz block TMVP (TBTMVP) using a suitable permutation matrix. Based on the TBTMVP representation, we have proposed a new (a, b)-way TBTMVP decomposition algorithm for implementing a digit-serial multiplication. Moreover, it is shown that, based on iterative block recombination, we can improve the space complexity of the proposed TBTMVP decomposition. From the synthesis results, we have shown that the proposed TBTMVP-based multiplier involves less area, less area-delay product, and higher throughput compared with the existing digitserial multipliers.

Original languageEnglish
Pages (from-to)735-746
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number2
DOIs
StatePublished - 1 Feb 2017

Keywords

  • Karatsuba algorithm
  • Shifted polynomial basis (SPB)
  • Toeplitz matrix-vector product (TMVP)

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