Low-complexity all-digital sample clock dither for OFDM timing recovery

You Hsien Lin*, Terng-Yin Hsu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

Based on phase adjustment, this work investigates a low-complexity all-digital sample clock dither (ADSCD) to perform coherent sampling for orthogonal frequency-division multiplexing (OFDM) timing recovery. To reduce complexity, only tri-state buffers are acquired to build a multiphase all-digital clock management (ADCM), which can generate more than 32 phases over gigahertz without phase-locked or delay-locked loops. Following divide-and-conquer search and triangulated approximation, the phase adjustment is simple but efficient, such that four preambles are adequate to make analog-to-digital (A/D) sampling coherent. Performance evaluation indicates that the proposed ADSCD can tolerate ±400-ppm clock offsets with 0.8∼1.3-dBsignal-to-noise ratio (SNR) losses at 8% PER in frequency-selective fading. Hence, this scheme involves a little overhead to ensure fast recovery and wide offset tolerance for OFDM packet transmissions.

Original languageEnglish
Article number5191027
Pages (from-to)1036-1042
Number of pages7
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume18
Issue number7
DOIs
StatePublished - 1 Jul 2010

Keywords

  • Low complexity
  • multiphase clock
  • orthogonal frequency-division multiplexing (OFDM)
  • phase adjustment
  • timing recovery

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