Low-capaeitance SCR with waffle layout structure for on-chip ESD protection in RF ICs

Chun Yu Lin*, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

Silicon-controlled rectifier (SCR) has been used as an effective on-chip ESD protection device in CMOS technology due to the highest ESD robustness. In this work, the waffle layout structure for SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection device can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs.

Original languageEnglish
Title of host publicationProceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007
Pages749-752
Number of pages4
DOIs
StatePublished - 2 Oct 2007
Event2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 - Honolulu, HI, United States
Duration: 3 Jun 20075 Jun 2007

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Conference

Conference2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007
CountryUnited States
CityHonolulu, HI
Period3/06/075/06/07

Keywords

  • Electrostatic discharges (ESD)
  • Radio-frequency integrated circuit (RF IC)
  • Silicon-controlled rectifier (SCR)

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    Lin, C. Y., & Ker, M-D. (2007). Low-capaeitance SCR with waffle layout structure for on-chip ESD protection in RF ICs. In Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 (pp. 749-752). [4266539] (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2007.380991