Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process

Yuan Wen Hsiao*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

9 Scopus citations

Abstract

Electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interface circuits in a 130-nm CMOS process is presented in this paper. First, the ESD protection diodes with different dimensions were designed and fabricated to evaluate their ESD levels and parasitic effects in gigahertz frequency band. With the knowledge of the dependence of device dimensions on ESD robustness and the parasitic capacitance, whole-chip ESD protection scheme were designed for the general receiver and transmitter interface circuits. Besides, an ESD protection scheme is proposed to improve the ESD robustness under the positive-to-VSS (PS-mode) ESD test, which is the most critical ESD-test pin combination. With a silicon-controlled rectifier (SCR) between the I/O pad and VSS, the clamping voltage along the PS-mode ESD current path can be reduced, so the PS-mode ESD level can be improved. Besides, the parasitic P-well/N-well diode in the SCR can provide the NS-mode ESD current path. Thus, SCR is the most promising ESD protection device in ESD protection design with low-capacitance consideration. The ESD protection scheme presented in this paper has been practically applied to an IC product with 2.5-Gb/s high-speed front-end interface.

Original languageEnglish
Pages (from-to)650-659
Number of pages10
JournalMicroelectronics Reliability
Volume49
Issue number6
DOIs
StatePublished - 1 Jun 2009

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