Lossless data compression core design for integrated space data and communication system-on-chip

Wai-Chi  Fang

doi:10.1109/ISCAS.2006.1692581

Lossless data compression core design for integrated space data and communication system-on-chip

Wai-Chi Fang^*

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A CCSDS-compliant lossless data compressor core for space data and communication system-on-chip designs has been developed to meet the increasing strong demands on high-bandwidth high-speed space data systems. This data compressor core is based on CCSDS lossless data compression standard and designed with space-qualified 150-nm CMOS technology. It occupies a compact chip area of about 700μm × 700 μm. The total power dissipation is 0.2 watts at a throughput rate of 66 Msamples/sec. This compressor core meets low-power, high-throughput, and user-transparent requirements and will be one of valuable silicon intellectual properties for developing next generation high-performance system-on-chip based space data and communication systems.

Original language	English
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	297-300
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2006.1692581
State	Published - 1 Dec 2006
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 21 May 2006 → 24 May 2006

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country	Greece
City	Kos
Period	21/05/06 → 24/05/06

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10.1109/ISCAS.2006.1692581

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title = "Lossless data compression core design for integrated space data and communication system-on-chip",

abstract = "A CCSDS-compliant lossless data compressor core for space data and communication system-on-chip designs has been developed to meet the increasing strong demands on high-bandwidth high-speed space data systems. This data compressor core is based on CCSDS lossless data compression standard and designed with space-qualified 150-nm CMOS technology. It occupies a compact chip area of about 700μm × 700 μm. The total power dissipation is 0.2 watts at a throughput rate of 66 Msamples/sec. This compressor core meets low-power, high-throughput, and user-transparent requirements and will be one of valuable silicon intellectual properties for developing next generation high-performance system-on-chip based space data and communication systems.",

author = "Wai-Chi Fang",

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doi = "10.1109/ISCAS.2006.1692581",

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Fang, W-C 2006, Lossless data compression core design for integrated space data and communication system-on-chip. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1692581, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 297-300, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 21/05/06. https://doi.org/10.1109/ISCAS.2006.1692581

Lossless data compression core design for integrated space data and communication system-on-chip. / Fang, Wai-Chi .

ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 297-300 1692581 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A CCSDS-compliant lossless data compressor core for space data and communication system-on-chip designs has been developed to meet the increasing strong demands on high-bandwidth high-speed space data systems. This data compressor core is based on CCSDS lossless data compression standard and designed with space-qualified 150-nm CMOS technology. It occupies a compact chip area of about 700μm × 700 μm. The total power dissipation is 0.2 watts at a throughput rate of 66 Msamples/sec. This compressor core meets low-power, high-throughput, and user-transparent requirements and will be one of valuable silicon intellectual properties for developing next generation high-performance system-on-chip based space data and communication systems.

AB - A CCSDS-compliant lossless data compressor core for space data and communication system-on-chip designs has been developed to meet the increasing strong demands on high-bandwidth high-speed space data systems. This data compressor core is based on CCSDS lossless data compression standard and designed with space-qualified 150-nm CMOS technology. It occupies a compact chip area of about 700μm × 700 μm. The total power dissipation is 0.2 watts at a throughput rate of 66 Msamples/sec. This compressor core meets low-power, high-throughput, and user-transparent requirements and will be one of valuable silicon intellectual properties for developing next generation high-performance system-on-chip based space data and communication systems.

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Lossless data compression core design for integrated space data and communication system-on-chip

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