Lossless data compression core design for integrated space data and communication system-on-chip

Wai-Chi  Fang*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A CCSDS-compliant lossless data compressor core for space data and communication system-on-chip designs has been developed to meet the increasing strong demands on high-bandwidth high-speed space data systems. This data compressor core is based on CCSDS lossless data compression standard and designed with space-qualified 150-nm CMOS technology. It occupies a compact chip area of about 700μm × 700 μm. The total power dissipation is 0.2 watts at a throughput rate of 66 Msamples/sec. This compressor core meets low-power, high-throughput, and user-transparent requirements and will be one of valuable silicon intellectual properties for developing next generation high-performance system-on-chip based space data and communication systems.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages297-300
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 21 May 200624 May 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period21/05/0624/05/06

Fingerprint Dive into the research topics of 'Lossless data compression core design for integrated space data and communication system-on-chip'. Together they form a unique fingerprint.

Cite this