Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

Xuejue Huang*, Phillip Restle, Thomas Bucelot, Yu Cao, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

23 Scopus citations

Abstract

A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed.

Original languageEnglish
Pages (from-to)457-463
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume38
Issue number3
DOIs
StatePublished - 1 Mar 2003

Keywords

  • Clock distribution
  • Inductance
  • Proximity effects
  • Timing analysis

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