Loop-Based Design and Reconfiguration of Wafer-Scale Linear Arrays with High Harvest Rates

Ming-Feng Chang, W. Kent Fuchs

Research output: Contribution to journalArticle

3 Scopus citations


Design and reconfiguration approaches for high harvest rates and parallel on-wafer diagnosis of linear arrays are described in this paper. The defect-tolerant designs employ multiplexors to switch intercell connections and guarantee that the wire length between any two logically adjacent cells is constant, independent of fault distribution. The designs are appropriate for implementing linear arrays of wafer-scale memory and processor architectures. The harvesting of fault-free cells into a linear array is a percolation process; there exists a critical cell yield such that the harvest rate drops to zero (approaches 100%) if the cell yield is below (above) the critical value. Finding a maximum-size linear array for a given set of fault-free cells is polynomial time solvable if only the interconnections between fault-free cells are utilized, but is NP-complete if the interconnections between all cells are utilized. A heuristic reconfiguration algorithm utilizing the interconnections between all cells is presented. Application of boundary scan to parallel testing and on-wafer diagnosis of the arrays is described.

Original languageEnglish
Pages (from-to)717-726
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Issue number5
StatePublished - 1 Jan 1991

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