Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

Shih Chieh Wu, Chieh Lo, Tuo-Hung Hou*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V D -biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers
DOIs
StatePublished - 16 Jul 2012
Event2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Hsinchu, Taiwan
Duration: 23 Apr 201225 Apr 2012

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)1930-8868

Conference

Conference2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012
CountryTaiwan
CityHsinchu
Period23/04/1225/04/12

Fingerprint Dive into the research topics of 'Logic/resistive-switching hybrid transistor for two-bit-per-cell storage'. Together they form a unique fingerprint.

Cite this