Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V D -biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.
|Title of host publication||2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers|
|State||Published - 16 Jul 2012|
|Event||2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Hsinchu, Taiwan|
Duration: 23 Apr 2012 → 25 Apr 2012
|Name||International Symposium on VLSI Technology, Systems, and Applications, Proceedings|
|Conference||2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012|
|Period||23/04/12 → 25/04/12|