TY - GEN
T1 - Logical effort models with voltage and temperature extensions in super-/near-/sub-threshold regions
AU - Chang, Ming Hung
AU - Hsieh, Chung Ying
AU - Chen, Mei Wei
AU - Hwang, Wei
PY - 2011/6/28
Y1 - 2011/6/28
N2 - The voltage-/temperature-induced delay estimation error of conventional logical effort is much more severe in near/sub-threshold region. In this paper, super-/near-/sub-threshold logical effort models are proposed to eliminate delay estimation error caused by voltage and temperature variations. These models establish over the four different nanoscale CMOS generations. They also take environmental parameter variations with wide supply voltage 0.1∼1V and full temperature -50∼125°C range into account. The simulation results are using UMC 90-nm, PTM 65-, 45- and 32-nm bulk CMOS technologies, respectively. The average absolute error among the three regions are only 6.01%, 4.12%, 8.01% and 6.55% for UMC 90-nm, PTM 65-, 45- and 32-nm technology, respectively. Proposed models extend the original high performance circuits design in super-threshold region to low power circuit design in near-threshold and sub-threshold regions. They are useful for future green electronics applications.
AB - The voltage-/temperature-induced delay estimation error of conventional logical effort is much more severe in near/sub-threshold region. In this paper, super-/near-/sub-threshold logical effort models are proposed to eliminate delay estimation error caused by voltage and temperature variations. These models establish over the four different nanoscale CMOS generations. They also take environmental parameter variations with wide supply voltage 0.1∼1V and full temperature -50∼125°C range into account. The simulation results are using UMC 90-nm, PTM 65-, 45- and 32-nm bulk CMOS technologies, respectively. The average absolute error among the three regions are only 6.01%, 4.12%, 8.01% and 6.55% for UMC 90-nm, PTM 65-, 45- and 32-nm technology, respectively. Proposed models extend the original high performance circuits design in super-threshold region to low power circuit design in near-threshold and sub-threshold regions. They are useful for future green electronics applications.
UR - http://www.scopus.com/inward/record.url?scp=79959510856&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2011.5783613
DO - 10.1109/VDAT.2011.5783613
M3 - Conference contribution
AN - SCOPUS:79959510856
SN - 9781424484997
T3 - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
SP - 213
EP - 216
BT - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Y2 - 25 April 2011 through 28 April 2011
ER -