Logical effort models with voltage and temperature extensions in super-/near-/sub-threshold regions

Ming Hung Chang*, Chung Ying Hsieh, Mei Wei Chen, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

The voltage-/temperature-induced delay estimation error of conventional logical effort is much more severe in near/sub-threshold region. In this paper, super-/near-/sub-threshold logical effort models are proposed to eliminate delay estimation error caused by voltage and temperature variations. These models establish over the four different nanoscale CMOS generations. They also take environmental parameter variations with wide supply voltage 0.1∼1V and full temperature -50∼125°C range into account. The simulation results are using UMC 90-nm, PTM 65-, 45- and 32-nm bulk CMOS technologies, respectively. The average absolute error among the three regions are only 6.01%, 4.12%, 8.01% and 6.55% for UMC 90-nm, PTM 65-, 45- and 32-nm technology, respectively. Proposed models extend the original high performance circuits design in super-threshold region to low power circuit design in near-threshold and sub-threshold regions. They are useful for future green electronics applications.

Original languageEnglish
Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages213-216
Number of pages4
DOIs
StatePublished - 28 Jun 2011
Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
Duration: 25 Apr 201128 Apr 2011

Publication series

NameProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
CountryTaiwan
CityHsinchu
Period25/04/1128/04/11

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