Logical effort model extension with temperature and voltage variations

Chun Hui Wu*, Shun Hua Lin, Her-Ming Chiueh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

The method of "Logical Effort Delay Model" allows designers to quickly estimate delay time and optimize logic paths. But the previous variances of logical effort models do not mention how to handle process, voltage, and temperature (PVT) variations appropriately, which may induce a serious misestimate. According to simulation results, delay time increases 21% while temperature increasing from 0°C to 125°C, and increases 2X while supply voltage decreasing from 1V to 0.5V in 90nm process. Thus a simple linear extended logical effort g, 1/g=(mtt+bt,)VDD+C, supporting for temperature t and supply voltage VDD variations is presented. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions. After validation, the accuracy of this new extended logical effort model can achieve about 90%.

Original languageEnglish
Title of host publication14th International Workshop on Thermal Investigation of ICs and Systems, THERMINIC 2008
Pages85-88
Number of pages4
DOIs
StatePublished - 22 Dec 2008
Event14th International Workshop on THERMal INvestigation of ICs and Systems, THERMINIC 2008 - Rome, Italy
Duration: 24 Sep 200826 Sep 2008

Publication series

Name14th International Workshop on THERMal INvestigation of ICs and Systems, THERMINIC 2008

Conference

Conference14th International Workshop on THERMal INvestigation of ICs and Systems, THERMINIC 2008
CountryItaly
CityRome
Period24/09/0826/09/08

Fingerprint Dive into the research topics of 'Logical effort model extension with temperature and voltage variations'. Together they form a unique fingerprint.

  • Cite this

    Wu, C. H., Lin, S. H., & Chiueh, H-M. (2008). Logical effort model extension with temperature and voltage variations. In 14th International Workshop on Thermal Investigation of ICs and Systems, THERMINIC 2008 (pp. 85-88). [4669884] (14th International Workshop on THERMal INvestigation of ICs and Systems, THERMINIC 2008). https://doi.org/10.1109/THERMINIC.2008.4669884