Logic and fault simulation by cellular automata

Yih-Lang Li*, Cheng Wen Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We propose a massively parallel architecture to speed up the logic and fault simulation. We use a 2-D cellular automata (CA) to implement the logic and fault simulation of combinational circuits. Our CA has six cell states, and operates in a pipelined fashion. Experimental results on ISCAS85 benchmark circuits show that our CA outperforms the previously reported parallel simulators. As to pure logic simulation, our CA performs up to 9.24 billion GEPS using a 20 MHz clock and 8-bit words as opposed to 5 billion GEPS.

Original languageEnglish
Title of host publicationProceedings of the European Design and Test Conference
Editors Anon
PublisherPubl by IEEE
Pages552-556
Number of pages5
ISBN (Print)0818654112
DOIs
StatePublished - 1 Jan 1994
EventProceedings of the European Design and Test Conference - Paris, Fr
Duration: 28 Feb 19943 Mar 1994

Publication series

NameProceedings of the European Design and Test Conference

Conference

ConferenceProceedings of the European Design and Test Conference
CityParis, Fr
Period28/02/943/03/94

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  • Cite this

    Li, Y-L., & Wu, C. W. (1994). Logic and fault simulation by cellular automata. In Anon (Ed.), Proceedings of the European Design and Test Conference (pp. 552-556). (Proceedings of the European Design and Test Conference). Publ by IEEE. https://doi.org/10.1109/EDTC.1994.326820