Linear time hierarchical capacitance extraction without multipole expansion

S. Balakrishnan*, J. H. Park, H. Kim, Yu-Min Lee, C. C.P. Chen

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

Recently, hierarchical capacitance extraction algorithms have been shown an efficient and accurate capacitance extraction algorithm. An improved algorithm is also proposed to remove its runtime dependency on the number of conductors by a combination of hierarchical and multipole expansion algorithm. In this paper, we show that with the introduction of hierarchical merging operation and supernode representation, we can achieve linear runtime and accuracy without involving multipole expansion. Experimental results show over 10X runtime improvement and 20X memory saving over the multipole approaches with comparable accuracy and better numerical stability.

Original languageEnglish
Pages98-103
Number of pages6
StatePublished - 1 Jan 2001
EventIEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001) - Austin, TX, United States
Duration: 23 Sep 200126 Sep 2001

Conference

ConferenceIEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001)
CountryUnited States
CityAustin, TX
Period23/09/0126/09/01

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    Balakrishnan, S., Park, J. H., Kim, H., Lee, Y-M., & Chen, C. C. P. (2001). Linear time hierarchical capacitance extraction without multipole expansion. 98-103. Paper presented at IEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001), Austin, TX, United States.