Linear low voltage nano-scale CMOS transconductor

Tien Yu Lo, Chung-Chih Hung*, Chi Hsiang Lo

*Corresponding author for this work

Research output: Contribution to journalArticle

6 Scopus citations


This paper presents a high linearity MOSFET-only transconductor based on differential structures. While a precise BSIM4 transistor model is introduced through analysis, the linearity can be improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. When the compensation utilizes transistors in subthreshold region, rather than the transistors in saturation region, the value of transconductance can be maintained. The circuit is fabricated in TSMC 0.18-μm CMOS process. The measurement results show 18 dB improvement of the proposed version, and 65 dB HD3 can be achieved for a 2.1 MHz 700 mV pp differential input. The static power consumption under 1-V power supply voltage is 183 μW. Measurement results demonstrate the agreement with theoretical analyses.

Original languageEnglish
Pages (from-to)1-7
Number of pages7
JournalAnalog Integrated Circuits and Signal Processing
Issue number1
StatePublished - 1 Jan 2011


  • Subthreshold
  • THD
  • Transconductor

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