We investigate dielectric reliability associated with vias in low-k dielectric interconnects. We show that the failure mechanism of vias is identical to that of damascene lines, and occurs at the interface between the low-k and Cu-capping layers. We develop a model to accurately simulate failure distributions of via and line-only structures based on the assumption that the minimum dielectric space (highest local field) determines failure times. Via structures ultimately limit dielectric reliability of circuits because of the space reduction associated with via overlay tolerance between metal levels. We compare voltage ramp and constant voltage testing techniques and demonstrate their equivalence for via-related dielectric reliability estimation.