Limitation of low-k reliability due to dielectric breakdown at vias

Shou Chung Lee*, A. S. Oates, Kow-Ming Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations

Abstract

We investigate dielectric reliability associated with vias in low-k dielectric interconnects. We show that the failure mechanism of vias is identical to that of damascene lines, and occurs at the interface between the low-k and Cu-capping layers. We develop a model to accurately simulate failure distributions of via and line-only structures based on the assumption that the minimum dielectric space (highest local field) determines failure times. Via structures ultimately limit dielectric reliability of circuits because of the space reduction associated with via overlay tolerance between metal levels. We compare voltage ramp and constant voltage testing techniques and demonstrate their equivalence for via-related dielectric reliability estimation.

Original languageEnglish
Title of host publication2008 IEEE International Interconnect Technology Conference, IITC
Pages177-179
Number of pages3
DOIs
StatePublished - 9 Sep 2008
Event2008 IEEE International Interconnect Technology Conference, IITC - Burlingame, CA, United States
Duration: 1 Jun 20084 Jun 2008

Publication series

Name2008 IEEE International Interconnect Technology Conference, IITC

Conference

Conference2008 IEEE International Interconnect Technology Conference, IITC
CountryUnited States
CityBurlingame, CA
Period1/06/084/06/08

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