This paper analyzes the leakage and delay of Ultra-Thin-Body (UTB) GeOI devices and logic circuits. The impact of temperature, channel thickness, gate length and input pattern dependence on the leakage/delay are studied. Compared with the subthreshold leakage dominated SOI devices/circuits, the band-to-band tunneling dominated leakage current of GeOI devices/circuits show less sensitivity to temperature, gate length and input patterns of logic circuits. At 300K and comparable delay, GeOI inverter with smaller band-gap shows larger leakage than the SOI inverter at Vdd1V, while exhibits lower leakage than the SOI inverter at Vdd0.8V. The leakage of GeOI two-way NAND is less sensitive to gate length and input patterns. At 400K, GeOI inverter shows both lower leakage and lower delay at Vdd0.61V compared with the SOI counterpart. The use of stacked GeOI transistors cannot reduce the band-to-band tunneling leakage; while the stacked GeOI transistors show larger subthreshold leakage current reduction compared with the stacked SOI transistors.