Leakage-delay analysis of Ultra-Thin-Body GeOI devices and logic circuits

Vita Pi Ho Hu*, Ming Long Fan, Pin Su, Ching Te Chuang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper analyzes the leakage and delay of Ultra-Thin-Body (UTB) GeOI devices and logic circuits. The impact of temperature, channel thickness, gate length and input pattern dependence on the leakage/delay are studied. Compared with the subthreshold leakage dominated SOI devices/circuits, the band-to-band tunneling dominated leakage current of GeOI devices/circuits show less sensitivity to temperature, gate length and input patterns of logic circuits. At 300K and comparable delay, GeOI inverter with smaller band-gap shows larger leakage than the SOI inverter at Vdd1V, while exhibits lower leakage than the SOI inverter at Vdd0.8V. The leakage of GeOI two-way NAND is less sensitive to gate length and input patterns. At 400K, GeOI inverter shows both lower leakage and lower delay at Vdd0.61V compared with the SOI counterpart. The use of stacked GeOI transistors cannot reduce the band-to-band tunneling leakage; while the stacked GeOI transistors show larger subthreshold leakage current reduction compared with the stacked SOI transistors.

Original languageEnglish
Title of host publicationProceedings of 2011 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2011
Pages32-33
Number of pages2
DOIs
StatePublished - 11 Jul 2011
Event2011 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2011 - Hsinchu, Taiwan
Duration: 25 Apr 201127 Apr 2011

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings

Conference

Conference2011 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2011
CountryTaiwan
CityHsinchu
Period25/04/1127/04/11

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