Layout verification has been proposed to improve the ESD (Electrostatic Discharge) and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the ESD/latchup sensitive layout can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.
|Number of pages||5|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA|
Duration: 7 Sep 1997 → 10 Sep 1997