Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries

Ming-Dou Ker*, Sue Mei Hsiao, Jiann Horng Lin

*Corresponding author for this work

Research output: Contribution to journalConference article

Abstract

Layout verification has been proposed to improve the ESD (Electrostatic Discharge) and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the ESD/latchup sensitive layout can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

Original languageEnglish
Article number5774221
Pages (from-to)125-129
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA
Duration: 7 Sep 199710 Sep 1997

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