Layout verification for submicron CMOS cell libraries to improve ESD/latchup reliability

Ming-Dou Ker*, Sue Mei Hsiao, Jiann Horng Lin

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

Layout verification has been proposed to improve the ESD and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the layout sensitive to the ESD or latchup events can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

Original languageEnglish
Pages343-347
Number of pages5
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
Duration: 3 Jun 19975 Jun 1997

Conference

ConferenceProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
CityTaipei, China
Period3/06/975/06/97

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