Layout verification has been proposed to improve the ESD and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the layout sensitive to the ESD or latchup events can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.
|Number of pages||5|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China|
Duration: 3 Jun 1997 → 5 Jun 1997
|Conference||Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications|
|Period||3/06/97 → 5/06/97|