Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process

Ming-Dou Ker; Chun Yu Lin; Tang Long Chang

doi:10.1109/VDAT.2011.5783551

Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process

Ming-Dou Ker^*, Chun Yu Lin, Tang Long Chang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.

Original language	English
Title of host publication	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages	374-377
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2011.5783551
State	Published - 28 Jun 2011
Event	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan Duration: 25 Apr 2011 → 28 Apr 2011

Publication series

Name	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Country	Taiwan
City	Hsinchu
Period	25/04/11 → 28/04/11

Access to Document

10.1109/VDAT.2011.5783551

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Ker, M-D., Lin, C. Y., & Chang, T. L. (2011). Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 (pp. 374-377). [5783551] (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011). https://doi.org/10.1109/VDAT.2011.5783551

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title = "Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process",

abstract = "Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.",

author = "Ming-Dou Ker and Lin, {Chun Yu} and Chang, {Tang Long}",

year = "2011",

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doi = "10.1109/VDAT.2011.5783551",

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series = "Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011",

pages = "374--377",

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note = "null ; Conference date: 25-04-2011 Through 28-04-2011",

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Ker, M-D, Lin, CY & Chang, TL 2011, Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process. in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011., 5783551, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, pp. 374-377, 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, Hsinchu, Taiwan, 25/04/11. https://doi.org/10.1109/VDAT.2011.5783551

Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process. / Ker, Ming-Dou; Lin, Chun Yu; Chang, Tang Long.

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 374-377 5783551 (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.

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Ker M-D, Lin CY, Chang TL. Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 374-377. 5783551. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011). https://doi.org/10.1109/VDAT.2011.5783551