Layout placement optimization with isolation rings for high-voltage VLSI circuits

Chih Wei Lee, Hwa Yi Tseng, Chi Lien Kuo, Chien-Nan Liu, Chin Hsia

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In the literature, there are many EDA works related to the layout placement of analog VLSI circuits. However, few of them are discussing about the placement of high-voltage VLSI circuits. Compared with typical circuits, the design of high-voltage circuits often requires isolation rings around transistors for better protection. Because isolation rings will occupy large chip area, it is necessary to develop proper EDA tools for the placement optimization with isolation rings to reduce the chip cost. In this paper, a placement optimization flow is proposed to consider both symmetry constraints and isolation rings for the layout automation of high-voltage circuits. Through changing the location of transistors inside every isolation rings, different shapes of isolation rings will be considered simultaneously during the placement algorithm to optimize the layout area. According to the experimental results, the proposed placement algorithm is able to reduce the chip area for high-voltage designs with isolation rings and still keeps the algorithm efficiency.

Original languageEnglish
Title of host publication2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509039692
DOIs
StatePublished - 5 Jun 2017
Event2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan
Duration: 24 Apr 201727 Apr 2017

Publication series

Name2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

Conference

Conference2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
CountryTaiwan
CityHsinchu
Period24/04/1727/04/17

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