Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

Wei Jen Chang*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

3 Scopus citations

Abstract

Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-μm and 0.25-μm CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-μm salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.

Original languageEnglish
Pages213-216
Number of pages4
StatePublished - 1 Dec 2004
EventProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan
Duration: 5 Jul 20048 Jul 2004

Conference

ConferenceProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
CountryTaiwan
Period5/07/048/07/04

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