Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

Chih Ting Yeh*, Yung Chih Liang, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.

Original languageEnglish
Title of host publicationProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Pages241-244
Number of pages4
DOIs
StatePublished - 8 Nov 2010
Event2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan
Duration: 26 Apr 201029 Apr 2010

Publication series

NameProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Conference

Conference2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
CountryTaiwan
CityHsin Chu
Period26/04/1029/04/10

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