Layout design considerations in MOS continuous-time integrated filters

Shirley Smith*, Mohammed Ismail, Chung-Chih Hung, Shu Chuan Huang

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

Analysis of two layout designs used in the realization of MOS continuous-time integrated filters is presented. The effect of MOS parasitic capacitances is thoroughly studied and compared in the two layout design techniques. It is found that one layout method performs well at high frequencies or high Q, at the expense of increased harmonic distortion in comparison with the other method. A tradeoff between transistor matching and sensitivity to MOS intrinsic parasitic capacitances is revealed. A set of performance graphs are developed with the ratio of parasitic to integrating capacitance, C p /C, as a parameter. These graphs are useful in the design of high performance MOS continuous-time integrated filters.

Original languageEnglish
Pages300-305
Number of pages6
StatePublished - 1 Dec 1994
EventProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems - Taipei, Taiwan
Duration: 5 Dec 19948 Dec 1994

Conference

ConferenceProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems
CityTaipei, Taiwan
Period5/12/948/12/94

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    Smith, S., Ismail, M., Hung, C-C., & Huang, S. C. (1994). Layout design considerations in MOS continuous-time integrated filters. 300-305. Paper presented at Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems, Taipei, Taiwan, .