Layout consideration and circuit solution to prevent EOS failure induced by latchup test in a high-voltage integrated circuits

Hui Wen Tsai, Ming-Dou Ker

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

This paper presented a practical industry case of electrical overstress (EOS) failure induced by the latchup test in high-voltage integrated circuits (ICs). By using proper layout modification and additional circuit, the unexpected EOS failure, which is caused by negative-current-triggered latchup test, can be successfully solved. The new design with proposed solutions has been verified in the 0.6-$\mu$ m 40-V Bipolar CMOS DMOS (BCD) process to pass the test for at least 500-mA trigger current, which shows high negative-current-latch-up immunity without overstress damage, compared with the protection of only the guard ring. Such solutions can be adopted to implement high-voltage-applicable IC product to meet the industry requirement for the mass production of IC manufactures and applications.

Original languageEnglish
Article number6226839
Pages (from-to)493-498
Number of pages6
JournalIEEE Transactions on Device and Materials Reliability
Volume14
Issue number1
DOIs
StatePublished - 1 Jan 2014

Keywords

  • Electrical overstress (EOS)
  • high-voltage CMOS
  • latchup
  • Regulator

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